adder Project Status
Project File: | Lab4.xise | Parser Errors: | No Errors
Module Name: | adder | Implementation State: | New
Target Device: | xc95288xl-6TQ144 | Errors: |
Product Version: | ISE 14.7 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: |  | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
Post-Fit Simulation Model Report |  |

Date Generated: 03/06/2018 - 09:44:20