Wysw1 Project Status (02/27/2018 - 10:44:14)
Project File: | Lab3.xise | Parser Errors: | No Errors
Module Name: | Wysw1 | Implementation State: | Synthesized
Target Device: | xc95288xl-6TQ144 | Errors: | X 1 Error (1 new)
Product Version: | ISE 14.7 | Warnings: | No Warnings
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Wt 6. mar 09:21:23 2018 | X 1 Error (1 new) | 0 | 0
Translation Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | Wt 6. mar 09:27:02 2018
Post-Fit Simulation Model Report |  |

Date Generated: 03/06/2018 - 10:28:33