| Wysw1 Project Status (02/27/2018 - 10:44:14) | |||
| Project File: | Lab3.xise | Parser Errors: | No Errors |
| Module Name: | Wysw1 | Implementation State: | Synthesized |
| Target Device: | xc95288xl-6TQ144 |
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X 1 Error (1 new) |
| Product Version: | ISE 14.7 |
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No Warnings |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wt 6. mar 09:21:23 2018 | X 1 Error (1 new) | 0 | 0 | |
| Translation Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | Wt 6. mar 09:27:02 2018 | |
| Post-Fit Simulation Model Report | |||